1. Field of the Invention
The present invention relates generally to integrated circuit package technology and, more particularly, to an enhanced capacity semiconductor device or package which includes an increased number of lands serving as I/O's, the lands being provided in a prescribed arrangement and exposed within a common exterior surface of the package body of the device.
2. Description of the Related Art
Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.
The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe may extend externally from the package body or may be partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die pad of the leadframe also remains exposed within the package body.
Leadframes for semiconductor devices or packages can be largely classified into copper-based leadframes (copper/iron/phosphorous: 99.8/0.01/0.025), copper alloy-based leadframes (copper/chromium/tin/zinc: 99.0/0.25/0.22), and alloy 42-based leadframes (iron/nickel; 58.0/42.0) according to the composition of the elements or materials included in the leadframe. Exemplary semiconductor devices employing leadframes include a through-hole mounting dual type inline package (DIP), a surface mounting type quad flat package (QFP), and a small outline package (SOP). In recent years, land grid array type semiconductor devices using leadframes have also been developed for use in certain applications.
The aforementioned semiconductor devices are particularly advantageous for their smaller size and superior electrical performance. In the electronics industry and, in particular, in high frequency applications such hard disk drives, digital television and other consumer electronics, there is an increasing need for exposed pad or land semiconductor devices of increased functional capacity, coupled with reduced size and weight. In view of this need, conventional leadframe structures as currently known and integrated into existing semiconductor devices often prove to be unsatisfactory. The present invention provides a semiconductor device which addresses the aforementioned needs by providing increased I/O with a reduced overall size. The semiconductor device of the present invention includes a leadframe having an increased number of lands which are provided in a prescribed arrangement and exposed within a common exterior surface of the package body of the device. The leadframe of the semiconductor device may be fabricated in accordance with standard, low-cost forming techniques, with sawing, punching, etching, or other material removal processes being completed during the fabrication of the semiconductor device to effectively electrically isolate various structural features from each other therein. These, as well as other features and attributes of the present invention will be discussed in more detail below.
Common reference numerals are used throughout the drawings and detailed description to indicate like elements.